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| Ordering number : EN6021 CMOS IC LC78602NE Compact Disc Player DSP with Built-in Microcontroller Overview The LC78602NE CMOS IC implements compact disc player signal processing, servo control, LED display, key input acquisition, and remote controller processing without requiring control by a separate microcontroller. The basic functions provided include demodulation of the EFM signal from the optical pickup, deinterleaving, error detection and correction, 8x oversampling digital filters, D/A converter (with built-in analog low-pass filter), LED driver, remote controller processing, key acquisition, and control processing. Thus this IC can provide excellent cost/performance characteristics when implementing a low-end CD player. Functions * Implements CD play/pause, disc stop, track selection, fast forward, reverse, repeat mode playback of 1 track or the whole disc, programmed play (setup, play, and clear) of up to 16 tracks, and random repeat play under the control of key input or remote controller input. symbol data. * Separates the subcode data from the EFM signal and outputs that data to the internal control processing block. * After applying a CRC check to the subcode Q signal, outputs that signal to the internal control processing block. * Buffers the demodulated EFM signal data in internal RAM and compensates for 4 frames of jitter due to disc speed fluctuations. * Performs unscrambling and deinterleaving by reordering the demodulated EFM signal data to the stipulated order. * Performs error detection and correction and flag processing (C1: dual errors, C2: dual errors) * The C2 flags are set based on the C1 flags and the result of the C2 processing, and the signal is interpolated or previous value hold is applied based on the C2 flags. Dual interpolation is adopted in the interpolation circuit. Previous value hold is applied if two or more consecutive errors are indicated by the C2 flags. * Performs track jump, focus start, disc motor start/stop, muting on/off, track count, and other operations under control of the internal control processing block. * Provides digital outputs. * Generates D/A converter input signals with continuity improved by 8x oversampling digital filters. * Includes on-chip third-order noise shaper delta-sigma D/A converters with built-in analog low-pass filter. * Digital deemphasis circuit * Adopts zero-cross muting. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN D1898RM (OT) No. 6021-1/11 LC78602NE Features * Package: 64-pin QFP * 5-V single-voltage power supply Package Dimensions unit: mm 3159-QFP64E [LC78602NE] SANYO: QFP64E(QIP64E) Equivalent Circuit Block Diagram Slice level control Synchronization detection EFM demodulation CLV digital servo Subcode separator QCRC VCO clock oscillator Clock control RAM address generator Interpolation and muting Bilingual support circuit C1 and C2 error detection and correction Flag processing Digital attenuator 8 x oversampling digital filters 1-bit DAC Digital output circuit Servo commander Crystal oscillator circuit Timing generator System control LED driver No. 6021-2/11 LC78602NE Pin Assignment Top view Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN VOUT Pd max Topr Tstg Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VSS + 0.3 VSS - 0.3 to VSS + 0.3 300 -20 to +75 -40 to +125 Unit V V V mW C C Allowable Operating Ranges at Ta = -20 to +75C, VDD = 4.5 to 5.5 V, VSS = 0 V Parameter Supply voltage Symbol VDD VIH1 High-level input voltage VIH2 VIH3 VIH4 VIL1 Low-level input voltage VIL2 VIL3 VIL4 Input level Operating frequency range Crystal oscillator frequency VIN1 VIN2 fOP fX Conditions VDD, XVDD, L/RVDD, VVDD Normal speed playback DEFI, 3 V/*5 V, TMOD, *RES, HFL, TES *KEYIN EFMIN PUIN, RMTSL1 to 3, REMOTE, CLOSE, DRF DEFI, 3 V/*5 V, TMOD, *RES, HFL, TES *KEYIN EFMIN PUIN, RMTSL1 to 3, REMOTE, CLOSE, DRF EFMIN: Slice level control XIN: Capacitor coupled input EFMIN XIN, XOUT 16.9344 Ratings min 4.5 0.7 VDD 0.8 VDD 0.6 VDD 0.8 VDD 0 0 0 0 1.0 1.0 10 typ max 5.5 VDD VDD VDD VDD 0.3 VDD 0.5 VDD 0.4 VDD 0.2 VDD Unit V V V V V V V V V Vp-p Vp-p MHz MHz No. 6021-3/11 LC78602NE Electrical Characteristics at Ta = -20 to +75C, VDD = 4.5 to 5.5 V, VSS = 0 V Parameter Current drain Symbol IDD IIH1 IIH2 Low-level input current IIL1 IIL2 Applicable pins VDD, XVDD, L/RVDD, VVDD DEFI, 3 V/*5 V, EFMIN, TMOD, HFL, TES, PUIN, *KEYIN, RMTSL1 to 3, REMOTE, CLOSE, *RES, DRF LASER, FSTA, EFBAL, SP8 DEFI, 3 V/*5 V, EFMIN, TMOD, HFL, TES, RMTSL2 to 3, REMOTE, *RES, DRF PUIN, *KEYIN, RMTSL1, CLOSE EFMO, CLV, TOFF, TGL, JP, LASER, FSTA, EFBAL, SP8, FSEQ, PCK, SLOF, SLED+, SLED-, EFLG, FSX, *AMUTE DOUT EFMO, CLV, TOFF, TGL, JP, FSEQ, PCK, SLOF, SLED+, SLED-, *DIG1, *DIG2, EFLG, FSX, *AMUTE *SEG1 to 8, *PROG, *RANDOM DOUT PDO, CLV, JP, *RANDOM PDO, CLV, JP, *RANDOM PUIN, *KEYIN, RMTSL1, CLOSE, *DIG1, *DIG2, *PROG *SEG1 to 8 LASER, FSTA, EFBAL, SP8 PDO PDO RISET = 68 k RISET = 68 k 64 -96 VIN = VDD VIN = VDD VIN = 0 V VIN = 0 V 250 -5 -25 -50 -100 500 Conditions Ratings min typ 35 max 55 5 1000 Unit mA A A A A High-level input current High-level output voltage VOH1 VOH4 VOL1 IOH = -1 mA IOH = -12 mA IOL = 1 mA IOL = 8 mA IOL = 12 mA VOUT = VDD VOUT = 0 V 0.8 VDD 0.9 VDD 0.2 VDD 0.2 VDD 0.1 VDD 5 -5 100 50 10 80 -80 96 -64 V V V V V A A k k k A A Low-level output voltage VOL2 VOL5 Output off leakage current IOFFH IOFFL RPU1 RPU2 Pull-down resistance Charge pump output current RPD IPDOH IPDOL Pull-up resistance 1-Bit D/A Converter Analog Characteristics at Ta = 25C, VDD = L/RVDD = 5 V, VSS = L/RVSS = 0 V Parameter Total harmonic distortion Dynamic range Signal-to-noise ratio Crosstalk Symbol THD+N DR S/N CT Applicable pins LCHO, RCHO LCHO, RCHO LCHO, RCHO LCHO, RCHO Conditions 1 kHz: 0dB data input 20kHz low-pass filter used (built-in AD725D) 1 kHz: -60dB data input 20kHz low-pass filter and A filter used (built-in AD725D) 1 kHz: 0dB data input 20kHz low-pass filter and A filter used (built-in AD725D) 1 kHz: 0dB data input 20kHz low-pass filter used (built-in AD725D) 86 90 80 Ratings min typ 0.025 88 92 82 max 0.04 Unit % dB dB dB Note: Measured in normal speed playback mode with the Sanyo 1-bit D/A converter block reference circuit. No. 6021-4/11 LC78602NE 1-Bit D/A Converter Output Block Reference Circuit Analog output Left channel (right channel) AD725D (Manufactured by Shibasoku Ltd.) Oscillator element Oscillator element: 16.9344 MHz The following oscillator elements are recommended CSA-309 No. 6021-5/11 LC78602NE Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pin DEFI 3 V/*5 V PDO VVSS ISET VVDD FR VSS EFMO EFMIN TMOD CLV HFL TES TOFF TGL JP LASER FSTA EFBAL SP8 VDD FSEQ I/O I I O -- AI -- AI -- O I I O I I O O O O O O O -- O PLL circuit pins Function Defect detection signal (DEF) input. (Must be connected to 0 V if unused.) Supply voltage selection input. (High: 3V operation, low: 5V operation) Internal VCO control phase comparator output Internal VCO ground. This pin must be connected to 0 V. PDO output current adjustment resistor connection Internal VCO power supply VCO frequency range adjustment Digital system ground. This pin must be connected to 0 V. Slice level control pins EFM signal output EFM signal input Pin state during reset -- -- Undefined -- -- -- -- -- Undefined -- -- Hi-Z -- -- High output Undefined Hi-Z Pulled down Pulled down Pulled down Pulled down -- Undefined Test input. This pin must be connected to 0 V. Disc motor control output. This is a 3-value output. Track detection signal input. This is a Schmitt input. Tracking error signal input. This is a Schmitt input. Tracking off output Tracking gain switching output. A low level output raises the gain. Track jump control output. This is a 3-value output. Laser control. A pull-down resistor is built in. FSTA control. A pull-down resistor is built in. EFBAL control. A pull-down resistor is built in. SP8 control. A pull-down resistor is built in. Digital system power supply Synchronizing signal detection output. Outputs a high level if the synchronizing signal detected from the EFM signal and the internally generated synchronizing signal match. EFM data playback clock monitor. 4.3218 MHz when the phase is locked. (Note that this output is only provided in test mode. This pin outputs a low level during normal mode operation.) Sled off control output Sled feed output Limit switch detection input. A pull-up resistor is built in. Digital output (EIAJ format) Unused pin. This pin must be left open. Segment output (8). A pull-up resistor is built in. Segment output (7). A pull-up resistor is built in. Segment output (6). A pull-up resistor is built in. Segment output (5). A pull-up resistor is built in. Segment output (4). A pull-up resistor is built in. Segment output (3). A pull-up resistor is built in. Segment output (2). A pull-up resistor is built in. Segment output (1). A pull-up resistor is built in. Digital system ground. This pin must be connected to 0 V. Unused pin. This pin must be left open. Common driver output (2). A pull-up resistor is built in. Common driver output (1). A pull-up resistor is built in. Program operation monitor. A pull-up resistor is built in. Key matrix input (1). A pull-up resistor is built in. Unused pin. This pin must be left open. Unused pin. This pin must be left open. Random mode indicator output (Low: random mode, high: modes other than random mode.) Remote controller identifier input (3). This pin functions as an output pin set to the low level during resets (when the *RES pin is low) and for a few milliseconds after the *RES pin switches to the high level. Therefore, applications that will set this pin high must connect an external pull-up resistor to this pin. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 PCK SLOF SLED+ SLED- PUIN DOUT NC *SEG8 *SEG7 *SEG6 *SEG5 *SEG4 *SEG3 *SEG2 *SEG1 VSS NC *DIG2 *DIG1 *PROG *KEYI1 NC NC *RANDOM O O O O I O -- O O O O O O O O -- -- O O O I -- -- O Low output High output Low output Low output -- Undefined -- Pulled up Pulled up Pulled up Pulled up Pulled up Pulled up Pulled up Pulled up -- -- Pulled up Pulled up Pulled up -- -- -- Hi-Z 48 RMTSL3 I/O Low output Continued on next page. No. 6021-6/11 LC78602NE Continued from preceding page. Pin No. 49 Pin EFLG I/O O Function Monitor for C1, C2, single, and double error corrections. (Note that this output is only provided in test mode. This pin outputs a low level during normal mode operation.) Outputs a 7.35 kHz synchronizing signal that is generated by dividing the crystal oscillator output. (Note that this output is only provided in test mode. This pin outputs a low level during normal mode operation.) Audio mute output signal Remote controller signal input Remote controller identifier input (2). This pin functions as an output pin set to the low level during resets (when the *RES pin is low) and for a few milliseconds after the *RES pin switches to the high level. Therefore, applications that will set this pin high must connect an external pull-up resistor to this pin. Left channel D/A converter output D/A converter power supply D/A converter ground. This pin must be connected to 0 V. Right channel D/A converter output Close switch detection input. A pull-up resistor is built in. Remote controller identifier input (1). A pull-up resistor is built in. Connections for a 16.9344 crystal element Crystal oscillator circuit power supply IC reset input. Applications must set this pin low temporarily when power is first applied. DRF input Pin state during reset Low output 50 51 52 FSX *AMUTE REMOTE O O I Low output Low output -- 53 RMTSL2 I/O Low output 54 55 56 57 58 59 60 61 62 63 64 LCHO L/RVDD L/RVSS RCHO CLOSE RMTSL1 XOUT XIN XVDD *RES DRF O -- -- O I I O I -- I I Undefined -- -- Undefined -- -- Clock output -- -- -- Note: The same potential must be connected to all the power supply pins (VDD, VVDD, L/RVDD, and XVDD). No. 6021-7/11 Sample Application Circuit LC78602NE No. 6021-8/11 Note: This circuit is an example of typical connections used with the LC78602NE, but is not a complete circuit, i.e. certain peripheral components and circuits have been omitted. Contact your Sanyo representative for detailed information on this circuit. LC78602NE Notes on Application Design It goes without saying that applications must strictly observe the absolute maximum ratings and allowable operating ranges (and recommended operating conditions) stipulated for this IC to achieve reliability as a system. However, we also strongly recommend that designers carefully consider both the mounting conditions and the actual usage environment, including ambient temperatures and static electricity, when designing applications. This section provides additional notes concerning design, mounting, and certain other points that require care during application design. 1. Handling of Unused Pins If any unused pins on this IC are left in the open state, certain internal states may become undefined. Unused pins for which the handling is specified in the documentation must be handled as specified. Also be sure that no output pins contact any power supply or ground lines or any other output pin. 2. Latch-up Prevention * Due to the internal structure of this IC, the same potential must be applied to all power supply pins. -- Also provide the same potential to the servo system ASP. Since the slice level control circuit is shared with this IC, the same power supply potential must be applied. Also be sure to apply the same potential to all ASP power supply pins. -- For products in which the power supply pins are completely isolated within the IC and special allowances apply, be sure to follow the detailed instructions in the documentation. * The IC may latch up if timing discrepancies appear between the rise times for different power supply pins. Design applications so that no discrepancies appear. * Do not raise the voltage of any input or output pin above the VDD level, and do not lower the voltage below VSS. This point requires special care when power is first applied. * Do not allow overvoltages or abnormal signal noise levels to be applied to this IC. * In general, latch-up can be prevented by tying unused input pins to VDD or VSS. However, the directions for unused pin handling in the documentation for this IC must be followed. * Do not short the outputs. 3. Interface When different devices are connected, incorrect operation may result if the input VIL and VIH and the output VOL and VOH levels do not match. Insert level shifters so that the IC is not destroyed if it is connected to a device that uses a different power-supply voltage, such as in a dual power supply system applications. 4. Load Capacitance and Output Current * If a load with a large capacitance is connected, the wiring may fuse since such a load can result in the equivalent of an output short for an extended period. Also, excessive charge and discharge currents can cause noise and degrade application performance or lead to incorrect operation. Use loads of the recommended capacitance. * Excessive output sink or source currents can lead to problems similar to those described above. Use this IC within the recommended current levels while taking the maximum allowable power dissipation into consideration as well. 5. Notes on Power Application and Reset * There are cases where care is required at power on, during a reset, and when the reset state is cleared. Refer to the specifications sheet for the product and observe the notes concerning power on and IC reset. * The pin output states, the pin I/O direction settings, and the contents of the registers are not guaranteed when power is first applied in this IC. Items that are defined by the reset operation and when the mode is set are guaranteed after that operation. Applications must first apply a reset to this IC after power is applied. Since pin states and register contents that are not defined by the reset operation may change over time from the states in early versions due to long term variations across lots, applications should not depend on these values. No. 6021-9/11 LC78602NE 6. Notes on Thermal Design The failure rate of semiconductor devices is accelerated by higher ambient temperatures and power dissipation levels. We strongly recommend taking changes in ambient conditions into account and providing as large a margin as possible in thermal design to assure high reliability. 7. Notes on Printed Circuit Board Pattern Design * Ideally, the influence of shared impedances should be minimized by separating the VDD and ground lines for each system. * Design VDD and ground lines to be as short and as wide as possible, and to have the lowest high-frequency impedance possible. Ideally, decoupling capacitors (0.01 to 1 F) should be inserted in each VDD/ground pair. These capacitor should be placed as close to the corresponding VDD pin as possible. It is also appropriate to insert capacitors of about 100 to 220 F between each VDD and ground as low-frequency filters. However, be careful not to use values that are too large for these capacitors, since that can result in latch-up. -- In the servo system, the reference voltage line (VREF) and the driver VCC and ground lines are handled in the same way. The driver ground line should be made especially wide. If at all possible, use the recommended driver pattern, which, being directly under the device, was also designed to provide a heat dissipation effect as well. -- If a current output pickup is used, locate the optical pickup element connector and the ASP RF input as close together as possible. Even if a voltage output type pickup is used, the I/V conversion resistor located at the ASP input should be located near the ASP RF input. * The EFM signal line should be made as short as possible, and should either be located away from adjacent lines or should be shielded from adjacent lines by VSS or VDD shield lines. Since the slice level control output (EFMO) can easily disrupt the EFM signal line, the resistor connected to the output pin should be located as close to the pin as possible. Note that reducing the value of this resistor increases the influence of radiation and cares must be taken for the output level when the value increases. * Cover the area around the crystal with the ground pattern. 8. Other Notes If you have any questions during the application design phase, do not hesitate to contact your Sanyo sales representative or the nearest Sanyo semiconductor sales office. This IC is specifically designed for use in CD players, and as such its specifications differ from those of generalpurpose product standard logic ICs. We recommend system debugging using the end product system itself and adopting failsafe system design if required by the application. No. 6021-10/11 LC78602NE Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 6021-11/11 |
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